Delay Efficient Kogge Stone Approach for Implementing Shift Registers By Using Pulsed Latches

This project proposes delay efficient architecture for shift registers by using pulsed latches instead of flip flops. By using latches instead of flip-flops the major factors area and power can be reduced. By considering the necessary delays in pulses for latches the timing problem latches can be reduced. For obtaining these delays counter has to incremented by 1. The proposed kogge stone adder architecture reduces the delay to maximum extent, and produces numerous variations between conventional adder architecture. The synthesis and simulation is carried out using XILINX ISE 12.3i and HDL is developed using VERILOG language.